This invention relates, in general, to semiconductor devices, and more particularly to a metal semiconductor field effect transistor (MESFET) structure.
FETs may typically be used in high voltage applications such as amplifiers and switching power supplies However, there are fundamental problems inherent in the design and performance of standard power FETs.
The incompatibility of geometry parameters in various regions of the device is detrimental. For high current and high gain, channel regions must be short and heavily doped with thickness limited only by practical values of gate pinchoff voltage. On the other hand, the drain region must be relatively large and lightly doped to drop large amounts of potential across wide depletion widths. These requirements force a compromise in the design and performance of lateral FETs fabricated from single doped layers on semi-insulating substrates. The design and performance compromise as well as the lateral gate and drain arrangement that results in electric field crowding at the electrode edges generally limit breakdown voltage to less than 50 volts. Accordingly, vertical device structures are much more conducive to very high voltage applications since the voltage absorbing layer between the gate and drain can be doped much lower than the channel layer, and the overlapping parallel arrangement of electrodes eliminates crowding effects.
Basic material parameters are also in conflict High carrier mobility is desired in the source and channel This directly influences saturation current levels and gain In the III-V material system, the high mobility compounds tend to have smaller band gaps. In contrast, wide band gap material is desired in the drain regions since avalanche breakdown voltage increases with band gap.
Another problem with power FET design is that for short channel devices, current saturates due to carrier velocity saturation rather than channel pinchoff as in long channel devices. In the saturation region, the potential and electrical field distribution are not fixed and the additional drain voltage is dropped along the channel forming domains of electronic accumulation and depletion. The results of these modifications to the potential and electric field distributions include elevated values of output conductance, gate-drain capacitance and decreased avalanche breakdown voltage. These are commonly referred to as short channel effects and are essentially due to unwanted coupling between the device region which determines current and gain attributes (channel) and the region which determines voltage attributes (gate-drain diode).
One approach to combatting short channel effects has been the addition of a Schottky contact between the gate and drain to essentially form a dual-gate device. The Schottky contact lies adjacent to the original gate and is unmodulated and typically tied to source potential. At drain voltages beyond current saturation, additional drain potential is dropped mostly between the Schottky contact and drain instead of reaching into the channel region under the gate. The Schottky contact shields the channel at high drain voltage and prevents short channel effects.
The use of a "second gate" for shielding has been moderately successful at increasing breakdown voltages of lateral gallium arsenide microwave FETs. An example of this type of vertical device structure is set forth in U.S. Pat. No. 4,805,003 issued on Feb. 14, 1989 to Holm et al. In this structure, the "second gate" comprises two sections of a buried layer that can act as a parasitic back gate on the surface channel. More importantly, depletion of the vertical channel between the layers beneath the first gate acts to shield the channel and surface gate at high drain voltage. The device thus acts as a dual-gate FET, but provides the additional ability to more independently optimize the parameters of each channel due to the vertical structure.
Although increased breakdown voltage has demonstrated the shielding effect, there are only a narrow range of dimensions which provide extension of breakdown voltage without lowering saturation current levels due to saturation between the buried layer sections of the "second gate". Furthermore, even though this region becomes totally depleted, its potential is not locked after saturation but increases due to depletion in the buried layer sections of the "second gate". This allows large potential drops and electric fields beneath the gate. The result is that avalanche breakdown initiated directly under the gate limits the drain voltage.
Accordingly, it would be highly desirable to have a power FET that results in lower output conductance, reduced gate-drain capacitance and increased values of breakdown voltage.